High density multiple digital signal connection interface with reduced cross talk
US6385252B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/34
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A high speed digital signal connection interface with reduced cross talk includes a multiple pin connector with disconnectable header and receptacle portions. The header is attached to a first set of signal carrying wire pairs communicating with a first signal processing unit. The receptacle is attached to a second set of signal carrying wire pairs communicating with a second signal processing unit. Within each of the first and second wire pair sets is a first wire pair subset carrying digital signals travelling in a first direction between the signal processing units, and a second wire pair subset carrying digital signals travelling in a second direction between the signal processing units. The first and second wire pair sets are attached to the corrector such that adjacent pin pairs of the connector carry only signals travelling in the same direction and such that connector pin pairs carrying signals travelling in opposite directions are not adjacent to each other. An impedance matching circuit is provided for each signal-carrying wire pair of the first and second wire pair sets. Each impedance matching circuit has a first side connected to one of the signal processing units and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.