System and method for cache process
US6385697B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache system, a non-FSA (Full-Set Associative) cash table such as a DM (Direct Mapping) cache table is coupled with an FSA cache table. Tag comparison for cache hit judgment is executed simultaneously in the two cache tables. The number of cache hits to each cache line of the FSA cache table is counted by an access counter, and an access count value concerning the cache hit count is stored in an access count area of each cache line. When a cache hit occurred to a cache line of the FSA cache table, the access count value of the cache line is incremented by 1. When a miss hit occurred to both cache tables, the access count values of all the cache lines of the FSA cache table are decremented by 1 at once. If miss hits occurred to both cache tables when the DM cache table has an invalid cache line corresponding to the index of input address data, data fetched from main memory due to the miss hits is written into the invalid cache line corresponding to the index. If the miss hits occurred when the DM cache table has no invalid cache line corresponding to the index and the FSA cache table is full of valid cache lines, data stored in the miss hit cache line of the DM cache table is t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.