Reconfigurable integrated circuit with integrated debussing facilities and scalable programmable interconnect
US6388465B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A number of enhanced logic elements (LEs) are provided to form a [FPGA] reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved [FPGA] IC may further comprise[s] a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.