Semiconductor integrated circuit
US6388474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | May 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.