Integrated circuit generating a voltage linear ramp having a low raise
US6388505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Dec 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit voltage ramp generator is presented. The circuit includes at least one operational amplifier having a non-inverting input terminal connected to a voltage reference, and having an output terminal coupled in a feedback relationship to an output terminal of the generator circuit. The ramp voltage generator further includes a first storage capacitance connected between the non-inverting input terminal of the operational amplifier and a ground reference, which is loaded by means of a second pumping capacitance connected in parallel to the first capacitance. The pumping and voltage generation is and controlled by a series of passgates coupled to clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.