MMIC folded power amplifier
US6388528B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Sep 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A MMIC power amplifier having a smaller die size and higher power output are realized with the improved amplifier and transistor geometry herein provided. In particular, transistors, such as FETs (field effect transistors) are displaced from a conventional FET geometry with alternating FETs being rotated in opposite directions. The inputs (gate pads) and outputs (drain pads) of two adjacent FETs may be “shared.” In a shared input configuration, a compensation network may be coupled to the input. The improved FET configuration reduces the number of splitting and combining networks by up to 50% over the prior art and the die area for a typical 4 watt power amplifier is reduced by 48-72% over the prior art. The improved amplifier configuration provides a multi-sectional configuration wherein one section may be the mirrored image of another. In a two section amplifier, the amplifier appears to be “folded.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.