Method and apparatus for cascading frequency doublers

US6388546B1 · kind B1 · utility

Assignees

• Her Majesty the Queen in the Right of Canada, as represented by the Minister Industry, through the Communications Research Center Canada · CA
• The Communications Research Laboratory of the Ministry of Posts and Telecommunications, Japan · JP

Inventors

• Masahiro Kikokawa · Tokyo, JP
• Malcolm G. Stubbs · Ottawa, CA

Key dates

• Filing date: Sep 3, 1999
• Grant date: May 14, 2002
• Expiry date: Sep 3, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03B19/18
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

This invention provides a multistage frequency multiplier having a plurality of frequency doublers. Each doubler incorporates a three-terminal transistor device and is connected to an adjacent doubler via an interstage network. The network comprises a transmission line having its electrical parameters selected to achieve conjugate impedance matching at the intermediate harmonic frequency generated by the corresponding doubler. This network also includes a quarter-wavelength open-ended stub for suppressing a main input frequency component received by the corresponding frequency doubler. A shunt resistor on the transistor gate is preferably used to stabilize the network. This interstage network simplifies overall circuit topology to reduce total circuit size, and provides increased drive power levels to permit broader bandwidth and stabilize required output level from a local oscillator. This invention is particularly useful in high-speed, large-capacity communications systems and in microwave and millimeter-wave radar applications.