Graphic translate engine, floating point arithmetic unit and floating point multiply-add calculation unit
US6388672B1 · kind B1 · utility
10Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1997 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.