Gate-coupled ESD protection circuit without transient leakage
US6388850B1 · kind B1 · utility
29Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), applied in an internal circuit and an input pad, both coupled with a first power line and a second power line, comprises a voltage clamp circuit and a voltage bias circuit. The voltage clamp circuit, with a transistor, connects to the second power line for clamping potential level through the voltage clamp circuit. The voltage bias circuit, with at least one diode coupled in series, connects to the voltage clamp circuit and the first power line for biasing the voltage clamp circuit to the second power line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.