Semiconductor integrated device and electronic apparatus mounted with the device
US6388924B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
By differentiating and using the signal that makes reference potential generation circuit become active (differentiating pulse generation block 1), and by operating the reference potential generation circuit for a certain period of time, the current consumption can be reduced in proportion to the frequency when the operation frequency is low. Also, unstable operation during high speed operation of the memory is prevented by using the differentiating pulse generation block 1 when the pulse width of an input signal is long, and by using a clock that is generated through an oscillator when the pulse width of the input signal is short.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.