Method and system for reduction of test time for analog chip manufacturing
US6388928B1 · kind B1 · utility
0Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2001 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | May 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Analog integrated circuits have their individual characteristics compensated by the settings of self-contained non-volatile memory elements. The settings of the memory elements are determined by repeatedly testing the possible values until an optimal one is chosen. The testing process is accelerated by eliminating the need to re-write the non-volatile memory for each value that is tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.