DRAM refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment
US6389497B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jan 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors. Additionally, the number of priority request lines can be dramatically reduced by requiring a requesting processor to de-assert a bus request upon detecting a priority request by another processor. The multi processor system also includes a distributed DRAM ref…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.