Signal control circuit for controlling signals to and from a subsidiary processing circuit
US6389522B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The comparator 31 in the address control circuit 30 compares the present address signal, presently outputted from the CPU 10, with the preceding address signal that is being presently maintained in the maintaining portion 32. When the number of bits, at which the present address signal changes from the preceding address signal, is greater than or equal to the reference value, and when the bit pattern in the present address signal coincides with the reference bit pattern, the falling edge timing of the column address strobe signal CAS, which is outputted from the memory controller 33 to the DRAM 20, is delayed, whereby the address signal reading timing of the DRAM 20 is delayed. Even when all the bits in the address simultaneously change and therefore noise occurs, error will not occur in the input or output of the address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.