Microprocessor allowing simultaneous instruction execution and DMA transfer
US6389527B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an SPRAM used to specific purposes other than cache, and an address generator generating virtual addresses for access to the DCACHE and the SPRAM. Because the SPRAM can load and store data by a pipeline of the LSU and exchanges data with an external memory through a DMA transfer, the present invention is especially available to high-speedily process a large amount of data such as the image data. Because the LSU can access the SPRAM with the same latency as that of the DCACHE, after data being stored in the external memory is transferred to the SPRAM, the processor can access the SPRAM in order to perform data process, and it is possible to process a large amount of data with shorter time than time necessary to directly access an external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.