Method and apparatus to synchronize a bus bridge to a master clock
US6389547B1 · kind B1 · utility
28Cited by
13References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 18, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Mar 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2101/622
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for synchronizing a bus bridge to a master clock comprising receiving a time stamp packet at an input clock register of the bus bridge, comparing the value of the input clock register to the value of an output clock register of the bus bridge, obtaining an error value of the output clock register from the comparison, and determining whether the error value is below a predetermined threshold are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.