Embedded logic analyzer for a programmable logic device
US6389558B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2000 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Jul 6, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99954
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for embedding a logic analyzer in a programmable logic device allows debugging of such a device in its actual operating conditions. A logic analyzer circuit is embedded within a PLD, it captures and stores logic signals, and it unloads these signals through an interface to be viewed on a computer. Using an electronic design automation (EDA) software tool running on a computer system, an engineer specifies signals of the PLD to be monitored, specifies the number of samples to be stored, and specifies a system clock signal and a trigger condition that will begin the acquisition of data. The EDA tool then automatically inserts the logic analyzer circuit into the electronic design of the PLD which is compiled and downloaded to configure the PLD. Using an interface connected between the PLD and the computer, the EDA tool communicates with the embedded logic analyzer in order to arm the circuit and to poll it until an acquisition has been made. The EDA tool then directs the logic analyzer to unload the data from its capture buffer and then displays the data on the computer. The logic analyzer circuit may then be rearmed to capture another sequence of sample values. The trigge…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.