Method and apparatus for invalid state detection
US6389586B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | May 14, 2002 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising determining a state machine design point from a plurality of state machine design point options, where one of the plurality of state machine design point options corresponds to a safe design point. Then, forming a safe state machine model, if the safe design point is the determined state machine design point; where the safe state machine model has valid state logic separated from invalid state logic. Another method comprising detecting an invalid state of a state machine with invalid state logic. Then, setting a state machine register to a valid state with the invalid state logic. Then, continuing valid state operation of the state machine with valid state logic, where the valid state logic is separated from the invalid state logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.