Method and apparatus for chip placement
US6389688B1 · kind B1 · utility
26Cited by
22References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53178
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accurately registering electronic chip bonding pads with substrate leads. Images are developed of different portions of the interface between the electronic chip and the substrate by reflecting collimated, parallel light from the bottom of the chip through transparent areas of the substrate. Image analysis of the composite, superimposed images from spaced positions containing the bonding pads and the leads provide a corrective positioning after which the electronic chip and substrate are brought into contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.