Method of fabricating micro electro mechanical system structure which can be vacuum-packed at wafer level
US6391673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Nov 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01P15/0802
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of fabricating a micro electromechanical system (MEMS) structure which can be vacuum-packaged at the wafer level is provided. The method includes the steps of forming a multilayered stack including a signal line on a first wafer; bonding a second wafer to the multilayered stack; polishing the first wafer to a predetermined thickness; forming a MEMS structure in a vacuum area of the first wafer and a pad outside the vacuum area, the MEMS structure and the pad being connected to the signal line; forming a structure in a third wafer to have space corresponding to the vacuum area of the MEMS structure; and bonding the third wafer to the polished surface of the first wafer in a vacuum state. For protection of the structure and maintaining a vacuum level required for operation, the fabricated structure is vacuum-packaged at the wafer level, thereby improving the yield of fabrication. In addition, since a special vacuum packaging process is not necessary, the fabrication can be simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.