Method of manufacturing an integrated capacitor onto a silicon substrate
US6391802B1 · kind B1 · utility
14Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Aug 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of manufacturing a capacitor integrated onto a silicon substrate, comprising a step of depositing a layer of first electrode, a step of depositing a layer of a dielectric material, a step of exposure of the dielectric layer to a plasma and a step of depositing a layer of second electrode. This creates the advantage of a design of capacitors with metallic electrodes having a good linearity versus voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.