Character line address counter clock signal generator for on screen displays
US6392650B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | May 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A character line address counter clock signal generator for generating a character line address counter clock signal for an on screen display (OSD) circuit used to selectively display a character image within an on screen display contained within a displayed screen image. The character image displayed within the OSD is maintained at a substantially constant image height regardless of the number of image lines contained within the overall displayed screen image. The character image lines for a base character image are displayed in accordance with a predetermined repetition sequence without requiring phase lock loop to generate a reduced character line address clock or requiring arithmetic computation to calculate each character line address. The subject character line address counter clock signal generator uses programmable counters to selectively divide the horizontal synchronization signal to produce a clock signal with an aperiodicity corresponding to the predetermined repetition sequence of selected base character image lines such that selected lines are used R times while other selected lines are used R+1 times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.