Priority encoder with multiple match function for content addressable memories and methods for implementing the same
US6392910B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A priority resolver for use in a CAM circuit priority encoder is provided. The priority resolver includes one or more priority resolver sub-units. Each priority resolver sub-unit includes an local hit (pehit) generation circuitry. The local hit (pehit) generation circuitry is configured to generate pehit data. Also provided as part of a priority resolver sub-unit is a resolve processing circuit that is coupled to the local hit (pehit) generation circuitry. The resolve processing circuit is configured to receive the pehit data and an enable signal. Preferably, the resolve processing circuit includes input gating circuitry. An output differentiator and gating circuit is further provided as part of the priority resolver sub-unit and is configured to receive an output of the resolve processing circuit. In this embodiment, the priority resolver sub-unit is implemented in one or more stages of the priority resolver, and each stage is configured to include one or more priority resolver sub-units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.