Semiconductor memory circuit
US6392940B1 · kind B1 · utility
1Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of word lines connected to a plurality of memory cells, a plurality of row address decode circuits having address input terminals, a first wafer burn-in signal terminal, and a second wafer burn-in signal terminal. The row address decode circuits activate all of the word lines when the first wafer burn-in signal and the second wafer burn-in signal are in an enable state. On the other hand, the row address decode circuits activate a subset of the word lines when the second wafer burn-in signal is in the enable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.