Asynchronous SRAM compatible memory device using DRAM cell and method for driving the same
US6392958B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Apr 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An easily implemented SRAM compatible memory device usable as a low power asynchronous SPRAM and a driving method therefor. The method for driving the SRAM compatible memory device includes the steps of (a) inputting a leading address designating at least one of the plurality of memory cells, (b) generating an address transition detection signal in response to the input leading address, (c) allowing a predetermined DRAM access time to elapse after generation of the address transition detection signal, (d) performing an access operation of the DRAM memory array for the duration of the DRAM access time after step (c), and (e) inputting a lagging address different from the leading address after the lapse of a predetermined SRAM access time from the leading address input time. The SRAM access time is equal to or longer than twice the DRAM access time. In the SRAM compatible memory device and the driving method therefor, a DRAM memory cell is operated twice within an access time of an SRAM access time, thereby being fully compatible with an asynchronous SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.