Virtual channel bus and system architecture
US6393506B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 1999 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Jun 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor system includes an on-chip, split-transaction bus with independent address/control and data buses. Arbitration and bus acquisition protocols are performed on the address/control bus. An arbiter arbitrates I/O requests and regulates concurrent ownership of the split-transaction bus by assigning a virtual channel to each bus request. Data bus access is granted to a virtual channel on a priority basis, s so as to utilize to a maximum extent the available bandwidth of the data bus. In one embodiment, the data bus is preempted by another virtual channel when current virtual channel using the data bus becomes idle due to, for example, latencies in the data stream. Rearbitration, however, is avoided when the interrupted data transfer resumes, owing to state information regarding the data transfer stored in the master and slave modules of each virtual channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.