Method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge
US6393508B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services. Each device 30 that has access to secondary PCI bus 42 is categorized into either first tier 101 or a second tier 102. The devices 30 in first tier 101 are provided more frequent opportunities to gain access to secondary PCI bus 42 than devices in low tier 102. Next, a pending transaction is recognized when an initiating device 30 that has been categorized into second tier 102 accesses secondary PCI bus 42 and attempts a transaction that crosses PCI to PCI bridge 38 to primary PCI bus 26. However, PCI to PCI bridge 38 is unable to complete the transaction on primary PCI bus 26. Therefore, PCI to PCI bridge 38 is unable to provide access to any other device 30 on secondary bus 42 until the pending transaction completes. Next, device 30 that initiated the pending transaction is categorized into first tier 101 until the pending transaction is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.