Paging method for DSP
US6393530B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor system includes a global bus (14) having associated therewith a global address space with a plurality of processor nodes (10) associated therewith. Each of the processor nodes (10) has a CPU (20) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. The global bus (14) has associated therewith an arbiter (412). Each of the processing nodes interfaces with a global register (410) which is operable to contain paging registers for each of the files. A portion of the memory space in the processing nodes is paged over to the global address space. To facilitate the upper address bits of the global address space they are stored in a paging register and then the arbiter (412) selects these upper address bits for output to the bus. The lower address bits are provided by the particular processor node that is accessing the global address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.