Error self-checking and recovery using lock-step processor pair architecture
US6393582B1 · kind B1 · utility
124Cited by
11References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 10, 1998 |
| Grant date | May 21, 2002 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.