Method for fabricating polysilicon TFT
US6395571B1 · kind B1 · utility
3Cited by
2References
45Claims
0Family size
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Key dates
| Filing date | Sep 20, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
Abstract
Fabrication of a polysilicon TFT having a lightly doped drain or offset structure. Fabrication includes forming a semiconductor layer, a gate insulating film, and a gate electrode on a substrate. Then, forming lightly doped impurity regions in the semiconductor layer on both sides of the gate electrode. Next, forming an insulating film having a thickness that gradually becomes thinner away from the gate electrode. Then, forming heavily doped impurity regions in the lightly doped impurity regions in the semiconductor layer on both sides of the gate, resulting in regions with continuously varied impurity concentrations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.