Methods for forming ground vias in semiconductor packages
US6395582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1999 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Oct 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A tape ball grid array (TBGA) semiconductor package having a one metal layer interconnect substrate is provided. Further provided is a method for making the TBGA package having electrical connection through the one metal layer interconnect substrate down to a ground plane. The method includes: (a) defining at least one via hole through the one metal layer interconnect substrate; (b) filling the at least one via hole of the one metal layer interconnect substrate with a first solder ball; (c) reflowing the first solder ball; (d) placing a second solder ball over the reflowed first solder ball; and (e) reflowing the second solder ball to attach the second solder ball to the reflowed first solder ball. The reflowed first solder ball and the reflowed second solder ball form a ground via connection to the ground plane of the TBGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.