System and method for combining integrated circuit final test and marking
US6396295B1 · kind B1 · utility
8Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1998 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jun 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/01
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.