Noise-shaped digital frequency synthesis
US6396313B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Nov 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator for automatic test equipment employs an improved technique for generating clock signals from a reference clock. To generate a desired clock signal, a clock generator produces a time-quantized signal having a period equal to an integer number of reference clock periods and equal to the desired clock period, plus or minus a quantization error. For each cycle of the desired clock signal, a noise-shaping requantizer processes the quantization error to generate noise-shaping signals. The noise-shaping signals then establish delay values of a variable pipeline delay. The variable pipeline delay adjusts each period of the time-quantized signal by an integer number of reference clock cycles, based upon the noise-shaped signals. The effect of noise shaping the quantization error and selectively delaying the time-quantized signal is to shift jitter in the time-quantized signal from relatively low frequencies to relatively high frequencies. A phase-locked loop can then be used to filter the remaining high-frequency jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.