Method and apparatus for receiving high speed signals with low latency
US6396329B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.