Low-frequency, high-gain amplifier with high DC-offset voltage tolerance
US6396343B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jan 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/261
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The instrumentation amplifier circuit of the present invention is particularly suited for amplifying ECG signals, rejecting common mode signals and removing a DC offset. The preferred embodiment of the present invention basically comprises a front-stage differential amplifier, and a common-mode rejection circuit. By employing a twin-T network, the front stage differential amplifier is able to simultaneously remove the DC offset and achieve high gain using standard off-the-shelf components. The common mode differential gain, however, is zero, which is the desired result. The common-mode rejection circuit removes the common-mode signal to yield only the amplified ECG signal. The present amplifier circuit has a much greater DC offset tolerance than the prior art amplifier while the Common Mode Rejection Ratio (CMRR), residual noise at the output, and the input dynamic range is comparable to that of the prior art amplifier. Moreover, it requires fewer operational amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.