Low-power, low-noise dual gain amplifier topology and method
US6396347B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | May 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a low-heightened power, low-heightened noise dual gain amplifier, first and second, transistors have their emitter-collector circuits connected in series between the ground and a bus voltage. A radio frequency input terminal is coupled to the bases of both transistors. The first transistor is connected across the ground and an output terminal and operated in the common emitter mode. The first transistor operates as a high gain amplifier. A second transistor is connected across the output terminal and a bus voltage. First and second switching transistors switch first and second biasing sources to render first and second amplifier transistors conducted for operation in the high gain or low gain mode. Additionally, a third switching transistor is ac coupled across the input terminals of the first and second amplifier transistors. The third switching transistor is biased along with the first switching transistor for selectively coupling the RF input to the high gain or low gain amplifying transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.