Embedded mechanism offering real-time self failure detection for an analog to digital converter
US6396426B1 · kind B1 · utility
28Cited by
9References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1999 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention describes a real-time failure detection system for the inputs of an analog-to-digital converter. A novel mechanism is proposed that provides recognition of an ADC input pin failure through the digital result obtained. The device includes a specific hardware architecture which can be added to any ADC core. This is especially useful in safety applications (where FMEA is a main concern), as it greatly increases the reliability of the analog data measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.