Front-end sampling for analog-to-digital conversion
US6396429B2 · kind B2 · utility
40Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jan 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sampleand-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.