Memory arrangement for exposure data used in multiple exposures and method for processing multiple exposures
US6396501B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1999 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Feb 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory aarrangement for exposure data used in multiple exposures stores gray level data which include a high bit portion and a low bit portion. The memory arrangement includes a first memory for storing the high bit portion of the gray level data and a second memory for storing the low bit portion of the gray level data. The first memory and the second memory can be controlled by separate chip selection control signals. Further, the memories are provided with two separate byte enable signals, respectively, to control accesses to a high byte and a low byte in each memory unit. In writing, the gray level data are written in an interleaving manner to avoid conflicts between data lines. In reading, the high byte and the low byte which are interleaved are exchanged before they are read out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.