Method and apparatus for combining serial data with a clock signal
US6396877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1998 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jan 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B14/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The number of separate signals necessary in a serial interface are reduced by combining a transmit data signal with a clock signal having a rate equal to a multiple of a bit rate of the transmit data signal, before encoding for transmission. The number of separate signals in a serial interface may be reduced further by sigma-delta (&Sgr;/&Dgr;) encoding the transmit data into 1-bit samples, thus eliminating the need for a frame sync signal. By combining the transmit data with a higher rate clock signal, jitter in the recovered clock signal at the receiving end is greatly reduced or even eliminated. At the receiving end, the higher speed clock is recovered at the multiplied rate, used to latch the transmit data from the combined data and higher clock signal, and divided back to the data rate to provide an original bit clock along with an original transmit data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.