Bus arbitration system
US6397281B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a memory and a plurality of control logic sections interconnected through an arbitration bus. Each one of the control logic sections is coupled between a corresponding one of the control/data buses and the memory. Each one of such control logic sections includes a control logic for controlling transfer of data between the memory and the one of the plurality of control/data buses coupled to said one of the logic sections. The control logic is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic. Each one of the control logic sections also includes a bus arbitration section coupled to the arbitration bus. Each one of the bus arbitration sections is adapted to: (1) receive a control/data bus request from the control logic in such one of the control logic sections and from the other control logic sections coupled to such arbitration bus; (2) grant access to the control/data bus t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.