Preventing access to secure area of a cache
US6397301B1 · kind B1 · utility
33Cited by
14References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Information in a cache that is coupled to a processor is secured by recording the location in the cache of information that is being secured, and performing a cache avoidance procedure instead of allowing the instruction to access the area of the cache containing the information being secured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.