Method and apparatus for controlling shared memory access
US6397305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0837
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores words prior to writing them in the common memory, and a cache for receiving words from the common memory. The common memory is mapped twice into the address space of the first processor so that, in a first mapping, the first processor accesses the common memory directly and in a second mapping, the cache is enabled. The common memory can therefore be directly accessed with the first processor and the second processor when they share data that is read from or written into the common memory. The cache is accessed with the first processor in the second mapping for reading and writing data local to the first processor. Information written into the write buffer is tagged and the tagged information is flushed into the shared memory before the shared memory can be accessed by the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.