Memory subsystem operated in synchronism with a clock
US6397312B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1997 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Nov 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a simple configuration capable of high-speed data transmission is disclosed. Data is output from a controller or a memory in synchronism with a clock or a data strobe signal. The clock or the data strobe signal is transmitted by a clock signal line or a data strobe signal line, respectively, arranged in parallel to a data signal line. A delay circuit delays by a predetermined time the signals transmitted through the clock signal line or the data strobe signal line. The clock or the data strobe signal thus assumes a phase suitable for retrieval at the destination, so that the data signal can be retrieved directly by means of the received clock or the received data strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.