Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file
US6397324B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2000 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Jun 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers. The present approach provides an efficient mechanism for supporting these functions while maintaining separate compute and address register files.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.