Fault tolerant bus for clustered system
US6397345B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1998 |
| Grant date | May 28, 2002 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a plurality of interdependent processors. Each interdependent processor executes an independent operating system image without sharing file system state information, and each interdependent processor further has a network access card with a first network connection and a second network connection. The computer system has a first active backplane coupled to each first network connection of each processor; a second active backplane coupled to each second network connection of each processor, the second active backplane operating in lieu of the first active backplane in case of a fail-over; and one or more peripherals connected to each of the first and second active backplanes and responsive to data requests transmitted over the first and second active backplanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.