Method to reduce the node contact resistance
US6399440B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Nov 22, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
Abstract
A process for eliminating an interface layer between a poly plug and a hemispherical silicon grain. A substrate comprising a conductive plug and a storage node opening is provided, and the storage node opening is located on the conductive plug. Then, a first conductive layer is formed conformably over the inside surface of the storage node opening and a hemispherical silicon grain layer is formed on the first conductive layer. Next, the hemispherical silicon grain layer and the first conductive layer is implanted and the substrate is annealed. The re-arrangement and re-crystallization of the interface layer can greatly reduce the resistance of the node contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.