Plasma etch techniques for fabricating silicon structures from a substrate
US6399516B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1999 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 29, 2019 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0778
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Provided is a method for producing a silicon element. A substrate configuration is provided that includes a silicon layer having a first face and a thickness corresponding to a specified thickness of the silicon element to be formed. The configuration includes a layer of an electrically-insulating material located below and adjacent to the silicon layer. A substantially vertical trench is etched from the first face in the silicon layer to a depth that exposes the insulating layer. Then the trench in the silicon layer is exposed to a gaseous environment that is reactive with silicon, to substantially lateral etch the silicon layer preferentially at the depth of the insulating layer along a surface of the insulating layer. This lateral etch is continued for a duration that results in release of a silicon element over the insulating layer. Also provided is a process for etching an angled trench in a silicon layer. Here, a substrate configuration is provided including a first silicon layer having at least one trench etched through the first silicon layer, and layer of an electrically-insulating material located below and adjacent to the silicon layer. The insulating layer includes an a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.