Semiconductor integrated circuit
US6399991B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Nov 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/765
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the guard ring section, four regions, p+ diffusion region, n+ diffusion region, n+ diffusion region, and p+ diffusion region, are formed to surround a hard macro and disposed in the order of this from the inside, and the inside two regions are disposed in an n well, and the outside two regions are disposed in a p well. A potential VSS is applied in the innermost p+ diffusion region and the outermost p+ diffusion region, and a potential VDD is applied in the two n+ diffusion regions disposed between these p+ diffusion regions. As a result, capacitors are formed between the n well and the p+ diffusion region formed in the n well, and between the p well and the n+ diffusion region formed in the p well, and therefore noise from outside is shielded, power source noise is absorbed, and malfunctions of the macro cell are prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.