Test system and manufacturing of semiconductor device
US6400173B1 · kind B1 · utility
72Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Oct 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.