Semiconductor integrated circuit device and method of laying out clock driver used in the semiconductor integrated circuit device
US6400182B2 · kind B2 · utility
1Cited by
9References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2000 |
| Grant date | Jun 4, 2002 |
| Priority date | — |
| Expiry date | Dec 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1735
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit, the number of rows of transistors in each of first driver circuits is increased or decreased using MOS transistors group in clock driver circuits regions arranged in an array, such as in portions of circuit cell regions into which a core region is divided, in order to supply clock signals to cell, such as a megacell, through a mesh of interconnected clock signal supply lines, in the core region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.